Career Openings in Irvine, CA

Please send resumes with cover letter to [email protected].

Staff Engineer, Analog Design

ASIC Verification Engineer

Staff Engineer, Analog Design

Staff Engineer, Analog Design for Solarflare Communications, Inc. in Irvine, CA to develop, verify and test high speed data converters. Bachelor's degree in electrical engineering or related field (willing to accept foreign education equivalent) as well as 8 years of CMOS analog IC design at the transistor level including experience with high-speed (>300 Msps) ADC/DACs design experience or, alternatively, a Master's degree and 5 years of experience as noted above.

Experience must include:

  • high-speed ADC and DAC design;
  • 10 gigabit Ethernet design;
  • full development lifecycle, including requirements definition, design, cell layout, verification, bench level chip testing;
  • Cadence design and simulation software;
  • extraction using Caliber software;
  • 28 nm process design;
  • PLL/DLL loop analysis using Matlab software;
  • lab equipment including oscilloscope, oscillator and spectrum analyzer;
  • temperature measurement circuit design and crystal oscillator design;
  • and debugging of analog mixed signal circuits.

Email [email protected] or submit resume to Solarflare Communications, Inc., ATTN: M. Abalos , 7505 Irvine Center Drive, Suite 100, Irvine, California 92618. Reference Position Number: 43

ASIC Verification Engineer (Location Irvine or India)

Responsibilities:

  • Candidate will be responsible for high speed ASIC design and verification for Network controller type ASICs. This includes all aspects of ASIC development flow micro-architecture to timing closure.

Requirements:

  • 10+ experience in the ASIC and design and verification methodology, with some experience in emulation platforms is a plus.
  • Candidate must have working experience of synthesis and timing closure using DC and PTsi.
  • Candidate should have a good background in networking protocols like Ethernet and TCP-IP, and PCIE protocols.
  • Experience in design using SystemVerilog, C/C++ programming and Perl scripting is a plus.
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