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Career Openings
At Solarflare, we believe new ideas are only as good as the people who create and implement them and our success rests directly on the quality of our people and the products we develop. So if you would like to be a contributing part of an exciting, forward thinking company, where challenging responsibilities give you an opportunity to develop your skills to the next level, please review our job openings and contact us.
ASIC Verification Manager | ASIC Verification Lead (PHY) | ASIC Design Engineer | Senior/Principle Systems Application EngineerASIC Verification Manager
Overall Description: Overall ownership of asic verification activities in both pre-tapeout and post-tapeout phase of Solarflare’s Controller/PHY products
- Line manager of verification team – responsible for staffing and development of team members.
- Managing and directing activities of the PHY/Controller asic verification team and contractors.
- Working with the verification lead in PHY/Controller team to define verification methodology and develop/maintain verification schedule
- Coordinating and tracking activities of other Solarflare groups and outside vendors.
Responsibilities
Line manager of verification team
- Staffing, coaching and career development of the verification team
- Personnel management and performance review of the verification team
- Define/Planning of verification resource for projects and managing contractor staffing if appropriate
- Manage interface with outsourcing verification partner, define task scoping and progress tracking/monitoring of outsource projects.
- Planning/Execution of verification activities for PHY/Controller product
- Responsible for architecting/defining verification strategy of PHY/Controller product; forward looking into verification challenges of Solarflare’s product roadmap.
- Development and maintenance of block/top level verification testbench
- Responsible for the definition and development for block/top level verification plan, coverage metrics.
- Develop verification schedule and responsible for on-time and prediction execution of verification activities
- Assist in ASIC architecture development to enhance efficient pre-tapeout and post-tapeout verification.
- Define, develop and maintain hardware verification/emulation platform, including platform / fpga design if necessary
- Drive digital EVT activities when PHY/controller chips return and assist validation team on digital characterization activities for controller/PHY.
Requirements
- 5 years plus of managing experience in asic verification with proven track record of delivering robust design on time with both in-house and outsource resources.
- 10 years plus of working experience with
- complex PHY designs having significant high performance datapath DSP core elements
- switch/controller designs having significant network protocol processing.
- Experience in defining chip-top verification methodology, verification environment development for large ASIC multi-million gate SOC design, with close interaction with DSP system/firmware team and system level software driver team.
- Working experience with design verification or solid understanding on
- Complex arithmetic design against bit-exact C system modeling
- Design requiring compliance to standard specification
- Design with embedded processor core
- Must be familiar with VMM/OVM or equivalent transactor based verification framework.
- Must have solid understanding of
- DSP concept/techniques including FFT, FIR/LMS, ECC
- Ethernet interface protocol including XAUI/XFI/SGMII & backplane protocol
- Advance PCIE protocol including Gen2, Gen3 PCIE standard and SRIOV
- Packet processing of TCP, IPv4, IPv6, ARP, UDP, iSCSI, FcoE
- Ethernet packet format and MAC functionality
- MacSec/IPSec operation
- Analog circuits behavior modeling
- TLM development and verification
- Exposure to 1GBaseT/10GBaseT Ethernet PHY and Ethernet Controller design including is highly desirable
Education: BSEE required; MSEE preferred.
ASIC Verification Lead (PHY)
Overall Description: Owner of Solarflare’s 10gbaset PHY asic verification in both pre-tapeout and post-tapeout phase
- Managing and directing activities of the controller asic verification team and contractors.
- Coordinating and tracking activities of other Solarflare groups and outside vendors.
Responsibilities
Pre-tapeout
- Responsible for architecting the chip level verification strategy at the functional, design and implementation level of our current and next generation PHY product.
- Assist in Phy asic architecture development to enhance efficient pre-tapeout and post-tapeout verification.
- Working with design team to develop ASIC’s overall verification plans.
- Develop and Maintain Simulation Verification Testbench.
- Develop verification schedule and lead verification effort.
- Responsible for implementing block, chip and system verification modules and writing the test plan.
- Regression suite setup and maintenance
- Create and Analyze coverage metrics or other verification metrics to ensure completeness
- Analyzing test failures and aiding in debugging logic designs.
- Develop and Maintain Hardware Verification/Emulation Platform, including platform / fpga design if necessary.
Post-tapeout
- Responsible for IC digital evaluation plan development and execution
- Responsible to assist validation team on IC digital characterization activities, platform development and execution.
Requirements
- 5 - 10 years plus experience in asic verification and working experience with complex PHY designs having significant high performance datapath DSP core elements and standard compliance interfaces.
- Experience in defining chip-top verification methodology, verification environment development for large ASIC multi-million gate SOC design, with close interaction with DSP system/firmware team.
- Working experience with design verification on
- Complex arithmetic design against bit-exact C system modeling
- Design requiring compliance to standard specification
- Design with embedded processor core - Must be familiar with Verilog/System_verilog, common RTL and gate level simulation and verification tools.
- Must be familiar with VMM or OVM based verilog environment
- Must have solid understanding of DSP concept/techniques including FFT, FIR/LMS, ECC and Ethernet interface protocol including XAUI/XFI/SGMII
- Good understanding of IC design fundamentals.
- Exposure to Ethernet copper PHY design including 1GBaseT/10GBaseT is highly desirable
- Experience with formal checking tools and assertions is highly desirable.
- Experience with programming languages: C/C++, PERL, PLI is desirable.
Education: BSEE required; MSEE preferred.
ASIC Design Engineer
Responsibilities
- Responsible for design, verification, implementation (ASIC) of advanced signal processing algorithms for the physical layer of high speed wired data communication networks
- Develop ASIC specification, architecture, and micro-architecture of SOC implementation signal processing and communications algorithms
- Development/simulation of RTL hardware implementations in Verilog
- Synthesis, gate level simulation, timing analysis, design for test, of complex digital ASICs
- Lab testing and debug
Requirements
- 5 years plus experience in developing, implementing, and testing high performance communications and Signal Processing ASIC products
- Experience mapping communications algorithms to hardware and understanding of system design tradeoffs for high volume applications.
- Must be familiar with signal processing circuit structure and architecture and high performance datapath arithmetic circuit design and optimization.
- Must have extensive RTL experience including design, verification, and synthesis.
- Must have strong UNIX-based EDA tool skills and in-depth knowledge of ASIC design flows.
- Must be familiar with reusable HDL coding styles and design for high volume manufacture
- Experience in bit-exact MATLAB and C/C++ based system simulation and evaluation a plus.
- Working experience in architecting and design of high-performance FIR, FFT structures is a plus.
- Familiarity with DSP and PHY layer communication protocols of 802.3 is a plus.
Education: BSEE required; MSEE/PhD preferred.
Senior/Principle Systems Application Engineer
Responsibilities
- Primary interface from Systems engineering team for customer application issues and developments for a 10GBASE-T system solution.
- Transceiver bring-up of a 10GBASE-T system with emphasis on performance improvement and startup algorithm development.
- Plan and conduct technical demonstrations. Coordination of board, IC and firmware components necessary for demonstrations.
- Participation in cross vendor interoperability testing.
- Hardware specification, test and debug of board level prototyping.
- Identify, troubleshoot and resolve issues to ensure compliance to standards including emissions and susceptibility.
Qualifications
- Demonstrable team leadership skills needed for cross-functional (among algorithm, systems and circuit designers) coordination of transceiver evaluation and operation
- Methodical debugging skills including use of design of experiment techniques and failure and root cause analyses
- Experience with embedded processors and firmware development. Able to troubleshoot, write and modify C based firmware code.
- Good understanding of communication theory, fundamentals of signal processing, and PLL operation.
- Strong hardware troubleshooting capability with working knowledge of oscilloscopes, spectrum analyzers, network analyzers, logic analyzers, waveform generators and Spirent/Ixia traffic generators.
- Experience with analog, RF circuits and high speed digital interfaces.
- Experience with Matlab with emphasis on signal processing for system simulation and data analysis.
- DSP knowledge in digital filters, adaptive equalization and crosstalk cancellers typical in wire line applications such as DSL and Ethernet.
- Past experience in copper based Ethernet or xDSL highly desirable.